Performing a constrained optimization to determine circuit parameters

ABSTRACT

One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter. Next, the system generates objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort. The system then uses the objective functions to generate a constraint expression, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter. Next, the system computes a trade-off curve using the constraint expression. The system then computes transistor sizes for the circuit path based on a selected point from the trade-off curve.

BACKGROUND

1. Field of the Invention

The present invention relates to techniques for improving circuit performance. More specifically, the present invention relates to a method for performing a constrained optimization to determine circuit parameters.

2. Related Art

The circuit in FIG. 1 illustrates the series of challenges facing the modern integrated circuit designer. Note that the circuit includes a path of N+1 gates with side loads. For the purposes of illustration, assume that a gate i has a drive strength x_(i). In addition, assume that both the drive strength (x₀) of gate 0 and the side loads are fixed.

The first challenge is finding the drive strengths x_(i), 0<i≦N, that minimize the transistor area A of this path under the constraint that the total path delay is at most D₀. A more general question is to find the minimal transistor area A(D₀) as a function of the delay constraint D₀. This “cost function” reveals to the designer how the cost in terms of transistor area behaves as a function of the delay constraint D₀. Knowing this cost function permits a designer to choose the best trade-off between area and path delay.

The inverse of the first challenge is to find the drive strengths x_(i), 0<i≦N, that minimize the path delay D of this path under the constraint that the total transistor area of the path is at most A₀. Here, the more general question is to find the minimal path delay D(A₀) as a function of the area constraint A₀. This cost function reveals to the designer how the cost in terms of minimum path delay behaves as a function of the area constraint A₀.

A different, but similar, challenge is to find the drive strengths x_(i), 0<i≦N, that minimize the energy dissipation E of the path under the constraint that the total path delay is at most D₀. For this problem, we want to find how the cost E(D₀) in terms of energy behaves as a function of the delay constraint D₀. Conversely, we also want to find how the minimum path delay D(E₀) behaves as a function of the energy constraint E₀.

Another challenge arises with a cyclic path. In the case of a cyclic path, the path delay becomes the cycle time and the function A(D₀) represents the transistor area for a constraint D₀ on the cycle time. Conversely, D(A₀) represents the minimum cycle time for the constraint A₀ on the transistor area.

Researchers have proposed multiple solutions to the above-described constrained circuit optimization problems. Unfortunately, the proposed solutions fall short in one aspect or another, thereby limiting their effectiveness for many applications of interest. For example, several of the proposed solutions employ over-inclusive or non-convergent modeling techniques, which lead to prohibitive run-times or outright failure in some applications.

Hence, what is needed is a method for performing a constrained optimization to determine circuit parameters in a manner which expediently and accurately converges on a useful solution.

SUMMARY

One embodiment of the present invention provides a system which performs a constrained optimization of circuit parameters. During operation, the system selects two circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter. Next, the system generates objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort. The system then uses the objective functions to generate a constraint expression, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter. Next, the system computes a trade-off curve using the constraint expression. The system then computes transistor sizes for the circuit path based on a selected point from the trade-off curve.

In a variation of this embodiment, generating objective functions involves creating a first expression A(x) for the first parameter of the circuit path and creating a second expression B(x) for the second parameter of the circuit path.

In a variation of this embodiment, the parameters of the circuit path can include area, path delay, energy consumption, or any circuit path parameter which is expressed using the theory of logical effort.

In a variation of this embodiment, the path delay through the circuit path includes wire delay.

In a variation of this embodiment, generating the constraint expression involves placing the objective functions into a constraint expression, performing a Lagrangian relaxation on the constraint expression, and modifying the constraint expression using the gradients of the objective functions. Following these operations, the constraint expression is ∇A(x)=−λ∇B(x), for all λ>0, and where λ is a Lagrangian multiplier.

In a variation of this embodiment, computing the trade-off curve involves solving the constraint expression for each Lagrangian multiplier in a set of Lagrangian multipliers and plotting the value of each solution of the constraint expression as a point on the trade-off curve.

In a further variation, solving the constraint expression involves using the iterative process of coordinate-wise descent.

In a variation of this embodiment, selecting a point on the trade-off curve involves selecting the point on the curve that corresponds to the desired relationship between the first circuit parameter and the second circuit parameter.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 illustrates a circuit path consisting of N+1 gates.

FIG. 2 presents a plot where the expression ∇A(x)=−λ∇D(x) is used to calculate the point that minimizes the area A(x) under the constraint that D(x)≦D₀ in accordance with an embodiment of the present invention.

FIG. 3 presents a plot of area A(x_(λ)) versus delay D(x_(λ)) for a finite range of values for λ in accordance with an embodiment of the present invention.

FIG. 4 illustrates a string of three inverters with one side load and one final load in accordance with an embodiment of the present invention.

FIG. 5 illustrates the coordinate-wise descent algorithm with λ=∞ along with a contour plot of the path delay as a function of the drive strengths x₁ and x₂ in accordance with an embodiment of the present invention.

FIG. 6 presents the area versus delay function for the example circuit shown in FIG. 4 in accordance with an embodiment of the present invention.

FIG. 7 illustrates a chain of C-elements connected in a ring in accordance with an embodiment of the present invention.

FIG. 8 illustrates a segment from a chain of C-elements in accordance with an embodiment of the present invention.

FIG. 9 illustrates the energy versus delay function for the example circuit in FIG. 8 in accordance with an embodiment of the present invention.

FIG. 10 illustrates a path with side loads and resistive wires in accordance with an embodiment of the present invention.

FIG. 11 presents a flow chart that illustrates the process of optimizing a first circuit parameter with a limitation based on a constraint associated with a second circuit parameter in accordance with an embodiment of the present invention.

Table 1 presents successive values for (x₁, x₂) of the coordinate-wise descent algorithm when λ=∞ in accordance with an embodiment of the present invention.

Table 2 presents successive values for (x₁, x₂) of the coordinate-wise descent algorithm when λ=∞ in accordance with an embodiment of the present invention.

Table 3 presents successive values for (x₁, x₂) of the coordinate-wise descent algorithm in accordance with an embodiment of the present invention.

DETAILED DESCRIPTION

The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.

The data structures and code described in this detailed description are typically stored on a computer readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. This includes, but is not limited to, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs) and DVDs (digital versatile discs or digital video discs), and computer instruction signals embodied in a transmission medium (with or without a carrier wave upon which the signals are modulated). For example, the transmission medium may include a communications network, such as the Internet.

Logical Effort

We solve the constrained optimization problems using ideas from the theory of logical effort. (see Ivan Sutherland, Bob Sproull, and David Harris. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann Publishers, Inc., 1999.) We express path delay, total transistor area for a path, and energy dissipation of a path by means of logical efforts of gates. Note that the drive strength of a gate i is denoted as x_(i), the logical effort of a gate's input is denoted as g_(i), and the gate's parasitic delay is denoted as p_(i).

We first look at path delay. We can relate the gate delay s_(i) of gate i and the gate's drive strength x_(i) as follows for 0≦i≦N: s _(i) *x _(i) =p _(i) *x _(i) +g _(i+1) *x _(i+1) +C _(i),  (1) where g_(N+1)=0 and x_(N+1)=0. (see [Ebergen 2004] J. Ebergen, J. Gainsley, and P. Cunningham. Transistor sizing: How to control the speed and energy consumption of a circuit. In Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pages 51-61. IEEE Computer Society Press, April 2004.) From this equation we can derive gate delay s_(i) for gate i as s _(i) =p _(i)+(g _(i+1) *x _(i+1) +C _(i))/x _(i). The path delay D(x) is simply the sum of all gate delays, which yields

$\begin{matrix} {{D(x)} = {{\sum\limits_{i = 0}^{N}p_{i}} + {\sum\limits_{i = 0}^{N}{C_{i}/x_{i}}} + {\sum\limits_{i = 0}^{N}{g_{i + 1}*{x_{i + 1}/x_{i}}}}}} & (2) \end{matrix}$ where x_(N+1)=0 and g_(N+1)=0.

In accordance with Ebergen 2004, the capacitance, delay, drive strength, and energy consumption for a path can be expressed in units that depend on the process technology. The unit for capacitance is Λ, which is the input capacitance of a minimum-sized inverter. The unit for delay is τ, which is the delay of an ideal inverter without diffusion capacitance driving an identical inverter. The unit for drive strength is Λ/τ, or capacitance per time unit. The unit for energy is ε, which is the energy dissipated by a minimum-sized inverter without diffusion capacitance driving an identical inverter.

Finding an expression for the total transistor area of a path is simpler than finding an expression for path delay. As a measure for the total transistor area of a path, we add all transistor widths of the gates and require that all transistors are of minimum length. Like the units for delay and energy, which are τ and ε respectively, we define the unit for area as the total transistor area of a minimum-sized inverter. We denote the unit of area with a. Note that with this definition, the area unit depends on the particular process technology. The properties we derive, however, do not depend on a particular process technology.

Because the total input capacitance of a gate is proportional to the total transistor width of a gate, we can represent the total transistor width of a single gate as Σ_(j)(g_(j,i)*x_(i))=(Σ_(j)g_(j,i))*x_(i), where j ranges over all inputs of gate i. Let us denote the sum of all logical efforts of inputs of gate i, also called the total logical effort of gate i, by tg_(i), that is, Σ_(j)g_(j,i)=tg_(i). With this definition, a measure for the total transistor area of all gates on the path as a function of the vector of drive strengths x is

${A(x)} = {\sum\limits_{i = 0}^{N}{{tg}_{i}*{x_{i}.}}}$

Finding an expression for the total energy dissipation of a path is also straightforward. A gate i spends an energy proportional to s_(i)*x_(i) driving the gate's output capacitance. The constant of proportionality is c, which is the energy dissipated by a minimum-sized inverter without any parasitics driving a copy of itself. The total energy dissipated by the path as a function of the vector x of drive strengths, where each gate drives the gate's associated output once, is

$\begin{matrix} {{E(x)} = {\sum\limits_{i = 0}^{N}{s_{i}*x_{i}}}} \\ {= {\sum\limits_{i = 0}^{N}{\left( {{p_{i}*x_{i}} + {g_{i + 1}*x_{i + 1}} + C_{i}} \right)\mspace{20mu}\left( {{from}\mspace{14mu}{eqn}\mspace{14mu}(1)} \right)}}} \\ {= {\sum\limits_{i = 0}^{N}\left( {{\left( {p_{i} + g_{i}} \right)*x_{i}} + C_{i}} \right)}} \end{matrix}$ assuming that g₀=0.

Given these expressions for path delay, area, and energy consumption, we can formulate our problems formally. The problem statement for area minimization under a delay constraint becomes:

-   -   find the vector of drive strengths x that minimizes A(x) subject         to the constraint that D(x)≦D₀.         The problem statement for delay minimization under an area         constraint becomes:     -   find the vector of drive strengths x that minimizes D(x) subject         to the constraint that A(x)≦A₀.         Similarly, the problem statement for energy consumption         minimization under a delay constraint becomes:     -   find the vector of drive strengths x that minimizes E(x) subject         to the constraint that D(x)≦D₀.         The problem statement for delay minimization under a energy         consumption constraint becomes:     -   find the vector of drive strengths x that minimizes D(x) subject         to the constraint that E(x)≦E₀.         Convex Optimization

Because each of the functions D(x), A(x), and E(x) are convex functions, each of the constrained minimization problems is a well known convex optimization problem. (see [Boyd 2004] Stephen Boyd and Lieven Vandenberghe. Convex Optimization. Cambridge University Press, 2004.) There are many general techniques to solve these optimization problems. We use the technique called Lagrangian relaxation. The problem for area minimization:

-   -   find x that minimizes A(x) subject to D(x)≦D₀,         is equivalent to the Lagrangian relaxation problem:     -   find x, λ>0 that minimizes A(x)+λ(D(x)−D₀).         Note that in the preceding expressions, the parameter A is the         Lagrange multiplier. There are various techniques used to solve         Lagrangian relaxation.

To construct the area-delay trade-off curve, we have to find the values A(D₀) for a series of values D₀. For each value of D₀ we can apply Lagrangian relaxation and find the values of x₀, λ₀>0 that minimize A(x)+λ(D(x)−D₀). The value of A(x₀) is then the value A(D₀) we are looking for. Instead of minimizing A(x)+λ(D(x)+D₀) over all x and λ for each choice of D₀, we apply a slightly different method. For each λ, we compute the value x_(λ) that satisfies ∇A(x)=−λ∇D(x),  (3) where ∇ denotes the gradient in x, the vector of first-order derivatives to x. The value x_(λ) minimizes the function A(x)+λD(x), where λ is fixed. Because the function A(x)+λD(x) is convex, any local minimum is the global minimum, and as a consequence the value of x_(λ) is unique. Furthermore, x_(λ) is the value that minimizes A(x) subject to D(x)≦D(x_(λ)). Finally, the value x_(λ) is also the value that minimizes D(x) subject to A(x)≦A(x_(λ)). Consequently, the points (A(x_(λ)), D(x_(λ))) are the points on the area-delay trade-off curve for all choices of λ>0.

To solve our constrained optimization problems we must find the gradients in x for the path delay, area, and energy consumption functions D, A, and E respectively. The only variables for an acyclic path are x₁ through x_(N). Recall that for an acyclic path, drive strength x₀ is fixed. For the total area A we have, for 0<i≦N,

$\left( {\nabla A} \right)_{i} = {\frac{\partial A}{\partial x_{i}} = {{tg}_{i}.}}$ For the total energy E we have, for 0<i≦N.

$\left( {\nabla E} \right)_{i} = {\frac{\partial E}{\partial x_{i}} = {p_{i} + {g_{i}.}}}$ These gradients are constant vectors, where the elements are sums of logical efforts. For the gradient of D, we find

$\left( {\nabla D} \right)_{i} = {\frac{\partial D}{\partial x_{i}} = {\left( {{g_{i}/x_{i - 1}} - {\left( {C_{i} + {g_{i + 1}*x_{i + 1}}} \right)/x_{i}^{2}}} \right).}}$ where g_(N+1)=0 and x_(N+1)=0. A Graphical Illustration

FIG. 2 presents a plot where the expression ∇A(x)=−λ∇D(x) is used to calculate the point that minimizes the area A(x) under the constraint that D(x)≦D₀ in accordance with an embodiment of the present invention.

Within FIG. 2 is a contour plot of a delay function D(x) of two variables x₁ and x₂ for a simple circuit (see the circuit in FIG. 4). The delay contours are shown as a series of nested deformed circles. Each delay contour indicates all points with the same path delay. Note that the increments of the contour values are 10% of the minimum value. The path delay around the minimum 12.6 is very flat. The gradient ∇D in a point on a delay contour is a vector that points in the direction of steepest increase, and the length of the vector indicates the size of the increase. The gradient in a point is always perpendicular to the tangent of the delay contour.

The area function is a linear function of x and its contours are straight lines. We have shown one area contour in FIG. 2 using a bold black line. Area contours with a higher value are further from the origin and area contours with a smaller value are closer to the origin. The gradient of the area function is a constant vector for all points (x₁, x₂).

Let us say that the delay constraint is D(x)≦13.9. We want to find the minimum area A(x) satisfying this delay constraint. We can find this point graphically by finding the contour for the area function that is closest to the origin and intersects the contour D(x)=13.9. In other words, we have to find the area contour that is closest to the origin and that touches the contour D(x)=13.9. In the point where both contours touch, their gradients are co-linear, but point in opposite direction, as illustrated in FIG. 2. This point is uniquely defined by the equation ∇A(x)=−λ∇D(x) for some λ>0 and D(x)=13.9.

Alternatively, fixing λ instead of D₀, there is a unique value x_(λ) that satisfies ∇A(x)=−λ∇D(x). The point (A(x_(λ)),D(x_(λ))) defines a point on the area—delay trade-off curve.

A similar reasoning applies for minimizing the total energy dissipation E(x) of a path under a delay constraint for the path. Then we find for each λ, the value x_(λ)that satisfies ∇E(x)=−λ∇D(x).  (4) Plotting the Trade-Offs

We can plot the area A(x_(λ)) versus delay D(x_(λ)) for all values of λ. FIG. 3 presents a plot of area A(x) versus delay D(x) for a finite range of values for λ in accordance with an embodiment of the present invention. This plot illustrates the trade-off between path delay and total area. The designer can find for each constraint (λ) for the path delay what the minimum area is, or for each area constraint what the minimum path delay is. For the chosen combination of path delay D(x_(λ)) and area A(x_(λ)), the vector x_(λ)gives the drive strengths of the gates on the path.

The tangent of the area versus delay function in the point (D(x_(λ)), A(x_(λ))) is −λ. In each point on the area versus delay curve, the value of λ indicates the trade-off between area and delay. A small change δ in D(x_(λ)) creates a change −λ*δ in A(x_(λ)). Conversely, a small change δ in A(x_(λ)) creates a change −δ/λ in D(x_(λ)). For example, in the point that corresponds to λ=1, we can trade one unit τ of extra delay for one unit a of less area.

Note that for λ approaching infinity, x_(λ) approaches the value that minimizes the path delay D(x) without any constraint. Alternatively, for acyclic paths, the value for x_(λ)that achieves the minimum path delay is finite, and thus the area for minimum path delay is finite. For cyclic paths, the minimum cycle time is unattainable for finite values of x_(λ). For cyclic paths, the area goes to infinity as the cycle time approaches the minimum cycle time. The minimum cycle time is an asymptote for the area versus delay function.

Because the delay function around the minimum path delay is typically very flat, the area versus delay curve typically has a long steep part close to the minimum path delay, as illustrated in FIG. 3. This part indicates that for a small change in path delay there can be a large change in area. In other words, a small decrease in path delay close to the minimum comes with a high cost in terms of increase in area.

Finding x_(λ) by Coordinate-Wise Descent

For a given λ, we find the vector x_(λ) that satisfies ∇A(x)=−λ∇D(x) by coordinate-wise descent. The method of coordinate-wise descent is simple and converges rapidly to the solution.

Initially the algorithm can start at any vector x. In absence of any good choice of start vector, you can use the vector x_(i)=1 for all 0<i≦N.

For each i from N to 1, the algorithm updates coordinate x_(i) using equation (3), where we assume that all variables except x_(i) are fixed. After each update of a variable in x_(N) through x₁, the function A(x)+λD(x) decreases or remains the same. After several rounds of updates, the variables x_(N) through x₁ rapidly approach the minimum of the function. When the relative change in each x_(i) is less than a prescribed tolerance, the algorithm terminates.

The algorithm calculates each update to variable x_(i), 0<i≦N, as follows. When only x_(i) is variable, equation (3) reduces to tg _(i)=−λ*(g _(i) /x _(i−1)−(C _(i) +g _(i+1) *x _(i+1))/x _(i) ²) where g_(N+1)=0 and x_(N+1)=0. Solving for x_(i) yields

$x_{i} = {\sqrt{\frac{C_{i} + {g_{i + 1}*x_{i + 1}}}{\left( {{tg}_{i}/\lambda} \right) + {g_{i}/x_{i - 1}}}}.}$ We call the right-hand side of this equation the “update function” for variable x_(i).

${{update}_{i}\left( {x_{i + 1},x_{i - 1},\lambda} \right)} = {\sqrt{\frac{C_{i} + {g_{i + 1}*x_{i + 1}}}{\left( {{tg}_{i}/\lambda} \right) + {g_{i}/x_{i - 1}}}}.}$ The algorithm (where x^((k)) is the k-th approximation of x_(λ)) is as follows: x ⁽⁰⁾:=1; k:=0; repeat k:=k+1; for i=N to 1 do x _(i) ^((k+1)):=update_(i)(x _(i+1) ^((k)) ,x _(i−1) ^((k+1)),λ)od until ∥x ^((k+1)) −x ^((k)) ∥<tol*∥x ^((k+1))∥; Note that if you want to start the algorithm with x_(i)=0, for all 0<i≦N. the above formulas must be rewritten to avoid division by 0.

When the path is a cycle, some updates are slightly different. First, the drive strength x₀ of gate 0 is no longer fixed, but variable. Consequently, the indices are from 0 through N. Second, because each of the gates 0 through N is part of a cycle, the addition in indices is modulo N+1.

When we want to find the minimum energy dissipation of a path under a delay constraint, we find for each λ the value x_(λ) that satisfies ∇E(x)=−λ∇D(x) where (∇E)_(i)=p_(i)+g_(i) for 0<i≦N. This condition is similar to that for area minimization. In other words, to find x_(λ) for energy minimization, we only need to substitute p_(i)+g_(i) for tg_(i) in the algorithm for area minimization.

Constraints for Drive Strengths

So far we have not put any constraints on the drive strengths. Drive strengths often have two types of constraints. First, drive strengths can assume only values between a lower bound L_(i) and upper bound U_(i), which may be specific to each gate i—L_(i)≦x_(i)≦U_(i). Second, drive strengths often assume only discrete values, rather than continuous values. How can we incorporate these two constraints?

Before we deal with the two constraints, we observe a property of the update function. The update function update_(i) for variable x_(i), is a monotonic function in x_(i+1), x_(i−1), and λ. This means that that for two points p0=(x0_(i+1), x0_(i−1), λ0) and p1=(x1_(i+1), x1_(i−1), λ1) if p0≦p1 then update_(i)(p0)≦update_(i)(p1). The monotonicity property still holds if we change the update function to

${{update}_{1}^{\prime}\left( {x_{i + 1},x_{i - 1},\lambda} \right)} = {\min\left( {U_{i},{\max\left( {L_{i},\sqrt{\frac{C_{i} + {g_{i + 1}*x_{i + 1}}}{\left( {{tg}_{i}/\lambda} \right) + {g_{i}/x_{i - 1}}}}} \right)}} \right)}$ for each 0<i≦N. The modified update function makes sure that the value after each update stays within the interval [L_(i), U_(i)].

The consequence of the monotonicity property for the modified update function is that for each value of λ and start vector x_(i) ⁽⁰⁾=L_(i), for each 0<i≦N, the approximation algorithm produces a monotonically increasing sequence x⁽⁰⁾≦x⁽¹⁾≦⁽²⁾≦ . . . . This sequence converges to x_(λ,i), unless for some i, x_(i) ^((k)) remains stuck at its lower bound L_(i) or its upper bound U_(i).

Similarly, we can start the approximation algorithm at the upper bounds, in which case the algorithm produces a monotonically decreasing sequence of drive strengths. In either case, each drive strength x_(i) remains within its interval [L_(i), U_(i)]. This handles the constraints for the upper and lower bounds.

We can exploit the monotonicity property even further. If we want to construct the trade-off curve between area and delay, for example, we must compute the values x_(λ) for a sequence of values λ0, λ1, λ2, . . . If this sequence of λ's is a monotonic sequence, then you can use the vector x_(λ0) as the start vector for approximating x_(λ1), and x_(λ1) as the start vector for approximating x_(λ2), and so on. Depending on whether the sequence of λs is an increasing or decreasing sequence, we must choose the lower bounds L_(i) or the upper bounds U_(i), respectively, as the initial start vector. This choice of start vectors of each λ speeds up the computation of the trade-off curve even further.

For purposes of the examples in this description, we consider all drive strengths to be continuous. To deal with discrete values for the drive strengths, we can round the drive strengths in x_(λ) to discrete values. Because of the rounding, we may choose suboptimal drive strengths. How much we loose in optimality depends on the resolution of the discrete drive strengths in the neighborhood of the optimal values and the gradients of the delay, area, and energy functions in the same neighborhood.

Alternatively we can compute lower and upper bounds for the discrete drive strengths that achieve the optimum. We compute the lower bounds for the optimum by always rounding downwards the update value for each x_(i) to nearest discrete drive strength in an monotonically increasing sequence. We compute the upper bounds for the optimum by always rounding upwards the update value for each x_(i) in a monotonically decreasing sequence. Often the gap between lower and upper bound for each drive strength is zero or very small.

AN EXAMPLE

FIG. 4 illustrates a string of three inverters with one side load and one final load in accordance with an embodiment of the present invention. Both loads associated with the circuit are 10 and drive strength x₀=1. The functions D(x) and A(x) are as follows: D(x)=(1+x ₁/1)+(1+10/x ₁ +x ₂ /x ₁)+(1+10/x ₂)A(x)=1+x ₁ +x ₂.

Let us compute the area versus delay function for this example. For each λ we have to find x_(λ) satisfying ∇A(x)=−λ∇D(x) where ∇A(x)=[1, 1]. Because all gates are inverters, we have g_(i)=1 and tg_(i)=1 for i=1, 2. The update functions for x₁ and x₂ are:

$x_{1} = {{\sqrt{\frac{10 + x_{2}}{\left( {1/\lambda} \right) + 1}}\mspace{70mu} x_{2}} = {\sqrt{\frac{10}{\left( {1/\lambda} \right) + {1/x_{1}}}}.}}$

Let us first calculate the minimum path delay. For this purpose we choose λ=∞. The update functions now simplify to: x ₁=√{square root over (10+x ₂)} x ₂=√{square root over (10*x ₁)}

Table 1 provides the successive values for (x₁, x₂) during the execution of the coordinate-wise descent algorithm. After only six steps, or three vector values, the algorithm yields values for (x₁, x₂) that are less than 1% from the actual minimum. The path delay is minimal for (x₁, x₂)=(4.05, 6.36) with a path delay of approximately 12.66τ. The area at the minimum is approximately (1+4.05+6.36)α=11.4α. The energy dissipation by the path at the minimum is approximately (1+2*4.05+10+2*6.36+10)ε=41.8ε. FIG. 5 illustrates the coordinate-wise descent algorithm with λ=∞ along with a contour plot of the path delay as a function of the drive strengths x₁ and x₂ in accordance with an embodiment of the present invention.

TABLE 1 Current Value Next Value x⁽⁰⁾ x⁽¹⁾ x⁽²⁾ x⁽³⁾ x₁ √{square root over (1 * (10 + x₂))} 1 1 3.63 3.63 4 4 4.04 x₂ √{square root over (x₁ + 10)} 1 3.16 3.16 6.02 6.02 6.32 6.35

Let us see how fast the algorithm converges to the final values of x₁ and x₂ when we choose λ=1. Table 2 gives the simplified update functions and the successive values for (x₁, x₂) during the execution of the coordinate-wise descent algorithm. The result after each step, viz., each update, appears in the next column. After only four steps, or two vector values, the algorithm yields values for (x₁, x₂) that are less than 1% from the actual solution. For λ=1, x_(λ)=(2.52, 2.68) and D(x_(λ))≈14.3τ, A(x_(λ))≈6.2α, and E(x_(λ))≈31.4ε. We can calculate that by paying about 13% in extra path delay, the area of the path goes down by more than 45%. The energy goes down by almost 25%.

TABLE 2 Cur- rent Value Next Value x⁽⁰⁾ x⁽¹⁾ x⁽²⁾ x⁽³⁾ x₁ √{square root over (1 * (10 + x₂)/2)} 1 1 2.47 2.47 2.52 2.52 2.52 x₂ √{square root over (10/(1 + 1/x₁))} 1 2.24 2.24 2.67 2.67 2.68 2.68

FIG. 6 presents an area versus delay function for the example circuit shown in FIG. 4 in accordance with an embodiment of the present invention. As seen in FIG. 6, the sequence of values for λ is λ_(i)=a^(i)*0.1 for i=0, 1, . . . , 15 where a⁵=10.

A Second Example

In this example we consider a network with cycles. We find the area versus delay function and the energy versus delay function for one segment of this chain of C-elements. FIG. 7 illustrates a chain of C-elements connected in a ring and FIG. 8 illustrates a segment from a chain of C-elements in accordance with an embodiment of the present invention.

When performing a constrained optimization on the circuit of FIG. 7, if we need to consider every gate in this chain of C-elements, the task is unmanageable. For our analysis purposes, however, we only consider the segment of FIG. 8, where terminals labeled A connect to each other and terminals labeled B connect to each other. Note that we labeled each input and output of a gate with the logical effort or parasitic delay of that terminal.

The delay function D(x) for this circuit is the cycle time of the cycle containing an inverter and two C-elements. The delay function is D(x)=(1+2*x ₂ /x ₁)+2*(2+(C _(L) +x ₁+2*x ₂)/x ₂). Note that the delay of a single C-element is 4+(C_(L)+x₁)/x₂.

Rather than computing the area and energy function of a complete cycle, we calculate the area and energy function of a single segment only. The area function for one segment consisting of a single C-element and an inverter is A(x)=x₁+(2+2)*x₂. The energy spent in a single segment consisting of one inverter and one C-element is E _(segment)(x)=s ₁ *x ₁ +s ₂ *x ₂ =(1*x ₁+2*x ₂)+(2*x ₂ +C _(L)+2*x ₂+1*x ₁) =2*x ₁+6*x ₂ +C _(L). The gradients for these functions are

${{\nabla D} = \begin{bmatrix} {{2/x_{2}} - {2*{x_{2}/x_{1}^{2}}}} \\ {{2/x_{1}} - {2*{\left( {C_{L} + x_{1}} \right)/x_{2}^{2}}}} \end{bmatrix}},{{\nabla A} = \begin{bmatrix} 1 \\ 4 \end{bmatrix}},{{\nabla E} = {\begin{bmatrix} 2 \\ 6 \end{bmatrix}.}}$

In addition, the update functions obtained from ∇E=−λ∇D are

$x_{1} = {{\sqrt{\frac{2*x_{2}}{{2/\lambda} + {2/x_{2}}}}\mspace{70mu} x_{2}} = {\sqrt{\frac{2*\left( {10 + x_{1}} \right)}{{6/\lambda} + {2/x_{2}}}}.}}$

If we want to know the minimum cycle time of this circuit, ∇D=0 must hold. This condition implies that x₁ ²=x₂ ² and x₂ ²=x₁*(C_(L)+x₁). For fixed C_(L)>0, this condition can only be satisfied for x₁, x₂→≈ and x₁/x₂→1. The minimum cycle time in that case is 1+2+2*(2+1+2)τ=13τ. This minimum cycle time is independent of the value of C_(L).

We can compare this minimum cycle time in the unconstrained case to the minimum cycle time in the case where all gates have equal delay. The minimum cycle time in the equal gate delay model is calculated as 3*4.56τ=13.68τ. (see Ebergen 2004.) We observe that the two minimum cycle times are not far apart.

The minimum cycle time of 13τ is unattainable: the energy dissipation becomes prohibitive as the cycle time approaches the minimum cycle time. Suppose we want to minimize the cycle time of the chain of C-elements and the energy dissipation of each segment. We choose to give equal weight to cycle time and energy dissipation. That is, we want to find the drive strengths x such that the gradients in the energy function and cycle time are the same, but of opposite sign. In other words, any small change in drive strengths x₁ and x₂ that causes an increase or decrease in cycle time is counterbalanced by the same decrease or increase, respectively, in energy. For our example we take C_(L)=10.

Because we give equal weight to cycle time and energy, we choose λ=1. We must solve ∇D=−∇E. Solving this equation by coordinate-wise descent, we find the values in Table 3. We find that for (x₁, x₂)=(1.06, 1.76), the value for energy E is 24.3ε and the value for cycle time D is 24.88τ. The gate delay for the inverter is 4.32τ and the delay for the C-element is 10.28τ.

TABLE 3 Current Value Next Value x⁽⁰⁾ x⁽¹⁾ x⁽²⁾ x⁽³⁾ x₁ √{square root over ((2 * x₂)/(2 + 2/x₂))}{square root over ((2 * x₂)/(2 + 2/x₂))} 1 1 1.01 1.01 1.06 1.06 1.06 x₂ √{square root over (2 * (10 + x₁)/(6 + 2/x₂))}{square root over (2 * (10 + x₁)/(6 + 2/x₂))} 1 1.65 1.65 1.75 1.76 1.76 1.76

FIG. 9 illustrates the energy versus delay function for the example circuit in FIG. 8 in accordance with an embodiment of the present invention. As seen in FIG. 9, the sequence of values for λ is λ_(i)=a^(i)*0.1 for i=0, 1, . . . , 10 where a⁵=10.

Including Resistive Wires

We can generalize our model by including resistive wires between gates. FIG. 10 illustrates a path with side loads and resistive wires in accordance with an embodiment of the present invention. Note that we represent wires between gates by means of pi models, and we have merged any side loads to the wire load before and after the resistor. The variables x_(i−1), x_(i), x_(i+1) represent drive strengths, C_(i−1,0), C_(i−1,1), C_(i,0), C_(i,1) represent fixed capacitances, and R_(i−1), R_(i) represent fixed resistances. We define C_(i) as the total side load of stage i, i.e., C_(i)=C_(i,0)+C_(i,1). When the wire load C_(w) is the only side load, then C_(i,0)=C_(i,1)=C_(w/2).

Recall that the units for drive strength and capacitance are κ/τ and κ respectively. Because resistance is the reciprocal of drive strength, also known as conductance, the units for resistance are τ/κ.

Because of the addition of resistive wires, we must add to the path delay D(x) the delays due to the resistance of the wire. We use the Elmore delay model to update the stage delay of each stage. For stage i we obtain for the stage delay s _(i) =p _(i)+(g _(i+1) *x _(i+1) +C _(i))/x _(i) +R _(i) *C _(i,1) +R _(i) *g _(i+1) *x _(i+1), where the terms R_(i)*C_(i,1)+R_(i)*g_(i+1)*x_(i+1) are the delays attributable to the resistance of the wire. The total path delay becomes

${D(x)} = {{\sum\limits_{i = 0}^{N}\left( {p_{i} + {R_{i}*C_{i,1}}} \right)} + {\sum\limits_{i = 0}^{N}{\left( {c_{i} + {g_{i + 1}*x_{i + 1}}} \right)/x_{i}}} + {\sum\limits_{i = 0}^{N}{R_{i}*g_{i + 1}*x_{i + 1}}}}$ where g_(N+1)=0 and x_(N+1)=0.

For the area function we consider the contributions of the fixed wires to be fixed. So the wires contribute only a fixed constant to A(x). The modified delay function and area functions are still convex functions in x, and thus our optimization approach still applies.

For the gradient ∇D we obtain for 0<i≦N

$\left( {\nabla D} \right)_{i} = {\frac{\partial D}{\partial x_{i}} = {\left( {{g_{i}/x_{i - 1}} - {\left( {C_{i} + {g_{i + 1}*x_{i + 1}}} \right)/x_{i}^{2}}} \right) + {R_{i - 1}*g_{i}}}}$ Because the modified area function has changed only by a fixed constant, the gradient ∇A remains the same.

We need to solve ∇A=−λ∇D, where the delay function is modified. For 0<i≦N, this equation reduces to tg _(i)=−λ*((g _(i) /x _(i−1)−(C _(i) +g _(i+1) *x _(i+1))/x _(i) ²)+R _(i−1) *g _(i)) where g_(N+1)=0 and x_(N+1)=0. Solving for x_(i) yields

$x_{i} = {\sqrt{\frac{C_{i} + {g_{i + 1}*x_{i + 1}}}{\left( {{tg}_{i}/\lambda} \right) + {g_{i}/x_{i - 1}} + {R_{i - 1}*g_{i}}}}.}$ This equation gives the update to coordinate x_(i) in each iteration. Note that this update function is very similar to the one without resistive wires: the only extra term is R_(i−1)*g_(i). The Process of Constrained Optimization

FIG. 11 presents a flow chart that illustrates the process of optimizing a first circuit parameter with a limitation based on a constraint associated with a second circuit parameter in accordance with an embodiment of the present invention.

The process starts with the definition of a circuit path (step 1100). Defining the circuit path means selecting a circuit path that requires optimization along with a circuit path parameter for optimization and a circuit path parameter to serve as a constraint on the optimization.

For purposes of illustration, we optimize the area of the circuit path while using the path delay as the constraining parameter. The goal is to minimize the total area of the path without causing the path to experience excessive delay.

Next, the system formulates objective functions for the chosen parameters based on the theory of logical effort (step 1101). For the purposes of illustration, assume that the objective function for path delay is D(x) and the objective function for area is A(x).

The system then computes a trade-off curve of optimal points (step 1102). In order to compute the trade-off curve, the system first expresses the objective functions in a constraint expression (step 1103).

Note that the constraint expression mathematically articulates the optimization. For this example, the constraint expression is “find x that minimizes A(x) subject to D(x)≦D₀” (where D₀ is the limit on the total delay of the path).

Next, the system simplifies the constraint expression (step 1104). The system first converts the constraint expression to an equivalent Lagrangian relaxation expression. The system then substitutes the gradients of A(x) and D(x) into the Lagrangian relaxation expression. Following these operations, the constraint expression is: ∇A(x)=−λ∇D(x), for some λ>0 (where λ is a Lagrangian multiplier).

The system then solves the constraint expression for a set of λvalues (step 1105) and plots the solutions in a trade-off curve (step 1106). Note that the solution of the constraint expression for each λ is the “optimal point” for that λ, where the area is reduced as much as possible while still maintaining the required maximum path delay of D₀.

Next, the circuit designer selects a point on the trade-off curve where the trade-off between area and path delay fits the requirements of the circuit (step 1107). The designer then computes the sizes for the transistors of the circuit path based on the selected point (step 1108).

The foregoing descriptions of embodiments of the present invention have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims. 

1. A method for performing a constrained optimization to determine circuit parameters, comprising: selecting two types of circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter; generating objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort, wherein logical effort is used to characterize one or more gates in the circuit path by computing each gate's driving capability relative to that of a reference inverter; generating a constraint expression from the objective functions, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter; computing and plotting a trade-off curve by solving the constraint expression, wherein the constraint expression is ∇A(x)=−λ∇B(x), for all λ>0, and where λ is a Lagrangian multiplier, A(x) is an expression for the first parameter of the circuit path, and B(x) is an expression for the second parameter of the circuit path; and computing transistor sizes for the circuit path based on a selected point from the trade-off curve.
 2. The method of claim 1, wherein the parameters of the circuit path include at least one of: area; path delay; energy consumption; or a circuit path parameter which can be expressed using the theory of logical effort.
 3. The method of claim 2, where the path delay through the circuit path includes wire delay.
 4. The method of claim 2, wherein generating the constraint expression involves: placing the objective functions into a constraint expression; performing a Lagrangian relaxation on the constraint expression; and modifying the constraint expression using the gradients of the objective functions.
 5. The method of claim 4, wherein computing the trade-off curve involves: solving the constraint expression for each Lagrangian multiplier in a set of Lagrangian multipliers; and plotting the value of each solution of the constraint expression as a point on the trade-off curve.
 6. The method of claim 5, wherein solving the constraint expression involves using the iterative process of coordinate-wise descent.
 7. The method of claim 1, wherein selecting a point on the trade-off curve involves selecting the point on the curve that corresponds to the desired relationship between the first circuit parameter and the second circuit parameter.
 8. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for performing a constrained optimization to determine circuit parameters, comprising: selecting two types of circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter; generating objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort, wherein logical effort is used to characterize one or more gates in the circuit path by computing each gate's driving capability relative to that of a reference inverter; generating a constraint expression from the objective functions, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter; computing and plotting a trade-off curve by solving the constraint expression, wherein the constraint expression is ∇A(x)=−λ∇B(x) for all λ>0, and where λ is a Lagrangian multiplier, A(x) is an expression for the first parameter of the circuit path, and B(x) is an expression for the second parameter of the circuit path; and computing transistor sizes for the circuit path based on a selected point from the trade-off curve.
 9. The computer-readable storage medium of claim 8, wherein the parameters of the circuit path include at least one of: area; path delay; energy consumption; or a circuit path parameter which can be expressed using the theory of logical effort.
 10. The computer-readable storage medium of claim 9, where the path delay through the circuit path includes wire delay.
 11. The computer-readable storage medium of claim 9, wherein generating the constraint expression involves: placing the objective functions into a constraint expression; performing a Lagrangian relaxation on the constraint expression; and modifying the constraint expression using the gradients of the objective functions.
 12. The computer-readable storage medium of claim 11, wherein computing the trade-off curve involves: solving the constraint expression for each Lagrangian multiplier in a set of Lagrangian multipliers; and plotting the value of each solution of the constraint expression as a point on the trade-off curve.
 13. The method of claim 12, wherein solving the constraint expression involves using the iterative process of coordinate-wise descent.
 14. The method of claim 8, wherein selecting a point on the trade-off curve involves selecting the point on the curve that corresponds to the desired relationship between the first circuit parameter and the second circuit parameter.
 15. An apparatus for performing a constrained optimization to determine circuit parameters, the apparatus comprising: a processor; a selection mechanism configured to select two types of circuit parameters associated with a circuit path, wherein the optimization is to be performed on the first circuit parameter while a limitation on second circuit parameter functions as a constraint on the optimization of the first circuit parameter; and an execution mechanism on the processor, wherein the execution mechanism configured to: generate objective functions which model the first circuit parameter and the second circuit parameter in terms of logical effort, wherein logical effort is used to characterize one or more gates in the circuit path by computing each gate's driving capability relative to that of a reference inverter; generate a constraint expression from the objective functions, wherein the constraint expression mathematically relates the optimization of the first circuit parameter to the constraint on the second circuit parameter; compute and plot a trade-off curve by solving the constraint expression, wherein the constraint expression is ∇A(x)=−λ∇B(x), for all λ>0, and where λ is a Lagrangian multiplier, A(x) is an expression for the first parameter of the circuit path, and B(x) is an expression for the second parameter of the circuit path; and to compute transistor sizes for the circuit path based on a selected point from the trade-off curve. 